Continuous scaling of the gate dielectric in metal-oxide semiconductor (MOS) devices, along with its undesired increase in leakage current, has resulted in the evolution of high-K/metal gate stacks. These stacks are constructed either by forming the gate first or forming the gate last. In the gate first approach, the gate stack typically includes an amorphous silicon (a-Si) electrode on the metal gate with high dielectric (high-K) material, and the a-Si is formed after the high-K/metal gate is formed.
Referring to FIGS. 1A and 1B, there are illustrated prior art high-K/metal gate stacks 100a, 100b formed using a gate first approach. The gate stack 100a illustrated in FIG. 1A is an ideal high-K/metal gate stack, while the gate stack 100b illustrated in FIG. 1B shows the actual structure of such a gate stack. During a-Si deposition, a thin layer of native oxide 102 forms at the a-Si/metal interface as shown in FIG. 1B. This oxide layer 102 increases the gate contact resistance and in particular, increases the AC Reff. AC Reff is a measure of resistance to alternating current.
In these prior art high-K/metal gate stacks 100a, 100b, the gate stack is disposed on a substrate 110, and the stacks typically include the following layers: silicon oxynitride (SiON) 120, hafnium silicon oxynitride (HfSiON) 130, lanthanum oxide (La2O3) 140, titanium nitride (TiN) 150 and amorphous silicon (A-Si) 160. The FET gate stack shown in FIGS. 1A, 1B is a typical gate stack for an nFET. For pFET, the lanthanum oxide could be replaced with a combination, such as TiN/Al/TiN. As will be appreciated, different manufacturers may utilize different gate stack structures with different high-K materials.
One method of reduce the oxide layer 102 is to control the oxygen flow during the a-Si deposition process. However, the AC Reff is still high. One method may be to utilize pre-doping in the a-Si gate. This may result in a reduction of AC Reff of about 150 ohms (at a fixed DC Reff when pre-doping is introduced in the a-Si region of a pFET). Another method is to increase the source/drain (S/D) doping, which effectuates an increase in doping within the a-Si region. This may result in a reduction of AC Reff of about 200 ohms (with increased doping of S/D regions in nFET).
The main reason to utilize pre-doping or an increase in S/D doping is to increase the doping at the a-Si/metal interface to reduce the gate contact resistance, Rco. The issue of gate contact resistance is analogous to the issue of diffusion contact resistance (diffusion Rco). Similarly, scaling is limited by diffusion Rco which is dependent on the schottky barrier height (SBH). Since diffusion Rco depends on SBH, reducing SBH will reduce diffusion Rco and improve device performance.
Current techniques developed by one or more of the inventors for reducing SBH at the S/D contacts employ impurity segregation at the silicide/semiconductor (e.g., NiSi/Si) interface. The segregated layer, which could use for example impurities like As, B, In, Sb, N, Cl, S, Se, Al, Dy, Yb, Yt, etc., either passivates the surface or creates interface dipoles to reduce the SBH.
Accordingly, there is a need for an improved fabrication process (and resulting devices) that lowers contact Rco (and decreases AC Reff) and improves device performance. Also needed is a high-K/metal/a-Si gate stack with a segregated layer structure (metal/a-Si) to reduce contact Rco.